1. Field of the Invention
The present invention relates generally to packaging of substrates for integrated circuits (ICs).
2. Background Art
Traditional high speed substrate packaging can include high speed differential pair circuits routed on a metal 1 (M1) layer, metal 2 (M2) layer ground (GND), and metal 3 (M3) layer power (PWR) type structure. A metal 4 (M4) layer, in traditional substrate packaging, includes only ball pads, or signal. More specifically, power and GND balls are typically placed in the areas around the high speed differential pairs. However, achieving higher speeds from these traditionally packaged ICs (e.g., 1 giga-hertz (GHz) or greater) is problematic.
Using the traditional substrate packaging structure noted above, the standard M4 layers cannot support the performance of higher speed chip applications. This is due, in part, to too many differential routes on the same layer, poor distribution of analog and core power, a need to increase package size to accomplish all differential pairs, and cross coupling between power and signal lines within the same block/layer.
What is needed, therefore, is a method and system to ameliorate the challenges of the traditional IC packaging. More particularly, what is needed is an IC packaging system and method for accommodating higher speed differential pair circuit applications.